Scheduling in Input-queued Cell-based Packet Switches

Input queuing switch architectures must be controlled by a scheduling algorithm, which solves contentions in the transfer of data units from inputs to outputs. Several scheduling algorithms were proposed in the literature for switches operating on fixed-size data units. In this paper we consider the case of packet switches, i.e., devices operating on variablesize data units at their interfaces, but internally operating on fixed-size data units, and we propose novel extensions of known scheduling algorithms. We show that, in the case of packet switches, input queuing architectures can provide advantages over output queuing architectures. 1 Input vs. Output Queueing In the recent past, significant research efforts were devoted by both the academic and the industrial communities to the design of efficient ATM switches for BISDN [1]. Those research activities brought on the market efficient chip-sets currently used as building blocks for high-performance Internet routers. As a consequence, for many advanced Internet routers, the switching fabric internally operates on cells, and input IP datagrams are internally segmented into ATM-like cells that are transferred to output interfaces, where they are reassembled into variable-size IP datagrams. Most of the old designs of the switching fabric, i.e., of the part of the switch that is in charge of the transfer of data units from input to output line interfaces, assumed an output queuing architecture. Input queuing switch architectures [2] have recently received increasing attention, and they are currently considered by many designers as the best solution when the line speed is pushed to technological limits. The main disadvantage of output queuing (OQ) is that both the switching fabric and the output queues in line cards must operate at a speed equal to the sum of the rates of all input lines. In applications where the number of interfaces is large or the line rate is high, this makes OQ impractical. With respect to input queuing (IQ) schemes, OQ has the advantage that delays through the switch can be more easily controlled, and the implementation of (concentrated) fair queuing algorithms at the output is relatively easy and well understood [3]. IQ schemes permit all the components of the switch (input interfaces, switching fabric, output interfaces) to operate This work was supported by a research contract between CSELT and Politecnico di Torino and by the Italian Ministry for University and Research at a speed which is compatible with the data rate of input and output lines. One of the reasons why IQ was almost ruled out by the research efforts of the ATM community is the performance reduction due to head-of-the-line blocking in the case of a single queue per input interface [4]. Recently, Virtual Output Queuing (VOQ) or Destination Queuing schemes, that largely reduce this problem, were proposed [5]: in each interface card, input buffers are organized into a set of isolated queues, each queue storing cells directed toward a specific output interface. A major issue in the design of IQ switches is that the access to the switching fabric must be controlled by some form of scheduling algorithm in order to avoid contention1. Several scheduling algorithms for IQ cell switches were proposed and compared in the literature [2], [7], [8], [9], [10], [11]. They provide performance close to OQ architectures. We consider some of these proposals, and develop novel variations to deal with variable-size packets; more precisely, we constrain the scheduling algorithm to deliver contiguously all the cells deriving from the segmentation of the same packet. In other words, variable-size packets are transformed into “trains of cells”, and the transfer of the cells belonging to the same train is scheduled in such a way that they remain contiguous in the delivery to the output card, i.e., they are not interleaved with the cells of another train. We shall see that this constraint permits significant savings in memory and complexity, since the reassembly of packets at the output becomes much easier. The performance of the considered scheduling algorithms, both in the case of cell scheduling and in the case of packet scheduling, will be compared by simulation. 2 Logical Architecture